1. Field of the Invention.
The present invention relates to electrically programmable read-only-memories (EPROMs) and, in particular, to a virtual-ground flash EPROM array that reduces the cell pitch in the X direction.
2. Discussion of the Related Art.
A flash electrically programmable read-only-memory (EPROM) is a non-volatile memory that, like conventional EPROMs and electrically-erasable programmable read-only-memories (EEPROMs), retains data which has been stored in the memory when power is removed and which, unlike conventional EPROMs and EEPROMs, can be selectively erased.
FIG. 1 shows a plan view that illustrates a portion of a "virtual-ground" flash EPROM array 10, such as the array described in U.S. application Ser. No. 07/988,293, filed by Albert Bergemont on Dec. 8, 1992, titled HIGH DENSITY CONTACTLESS FLASH EPROM ARRAY USING CHANNEL ERASE.
As shown in FIG. 1, array 10 includes a series of memory cells 12, a series of access transistors 14, and a series of field oxide regions FOX which separate both the vertically-adjacent memory cells and access transistors of the array. In addition, each memory cell 12 and each access transistor 14 in a column of memory cells and access transistors shares a source bit line SOURCE and a drain bit line DRAIN with the remaining memory cells and access transistors in the column, and with the memory cells 12 and access transistors 14 in the horizontally-adjacent columns.
Further, a series of metal bit lines MBL1-MBLn in FIG. 1 are utilized to contact the drain bit lines DRAIN so that each drain bit line DRAIN is contacted by one metal bit line MBL once every 64 cells. The source bit lines SOURCE, on the other hand, are not contacted by a metal bit line.
As also shown in FIG. 1, the memory cells 12 in a row of memory cells share a common word line 16. As is well known, the portion of the word line 16 which is formed over each memory cell 12 in a row of memory cells functions as the control gate of the memory cells in that row. Similarly, the access transistors 14 in a row of access transistors share a common access select line 18.
One of the major goals in the design of a virtual-ground flash EPROM is to reduce the area consumed by each cell of the array, thereby increasing the density of the array. Conventionally, the area of a cell is measured by the pitch of the cell in the X direction and the pitch of the cell in the Y direction.
The pitch of a cell in the X direction can be defined as the distance from one edge of a field oxide region to the same edge of a horizontally-adjacent field oxide region. Thus, as shown in FIG. 1, the X cell pitch can be defined by the distance D.sub.1 which represents the length of a field oxide region FOX, and by the distance D.sub.2 which represents the minimum spacing between horizontally-adjacent field oxide regions FOX.
The length of the field oxide regions FOX, in turn, is defined by the distance D.sub.3, which represents the width of a floating gate, plus the distances D.sub.4 and D.sub.5, both of which represent a misalignment width. In a conventional virtual-ground flash EPROM fabrication process, the misalignment widths D.sub.4 and D.sub.5 are required to assure that the floating gates will be formed over a portion of each of the vertically-adjacent field oxide regions FOX even if the floating gates are slightly misaligned.
Thus, if the floating gates could be precisely positioned, the misalignment widths D.sub.4 and D.sub.5 could be eliminated, thereby substantially reducing the pitch of the cells in the X direction. Therefore, there is a need for a process which precisely positions the floating gates over a portion of each of the vertically-adjacent field oxide regions FOX.